This invention relates to programmable logic devices. More particularly, this invention relates to redundant circuitry for programmable logic devices.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. Like all integrated circuits, programmable logic devices are susceptible to manufacturing defects. If the rate of defects in a production run is high, the yield of good parts will be low, thereby increasing the manufacturing cost of each good part. In order to increase yields, programmable logic devices may be provided with spare or redundant circuits. When a manufacturing defect is detected in a circuit on the programmable logic device, that defective circuit may be repaired by switching the redundant circuit into use in its place. Programmable logic devices that are repaired in this way operate identically to devices that were manufactured completely without defects. The user therefore need not be concerned with whether a device has been repaired or was manufactured without a defect.
Care must be taken, however, that the overhead in circuit resources that is required to implement a redundancy scheme on a programmable logic device does not unduly increase the cost of manufacturing the programmable logic device. If too many resources are used to implement redundancy, the benefits of redundancy may be lost.
In addition, it is important that the patterns of interconnection conductors used to route signals on the programmable logic device are arranged so that they can accommodate redundancy.
The programmable logic on a programmable logic device may be organized by grouping logic in regions of various sizes. For example, programmable logic devices may contain relatively small areas of logic referred to as logic elements. These logic elements may be grouped to form programmable logic regions. The programmable logic regions and associated programmable memory regions may be grouped to form programmable logic super-regions. Appropriate switching resources and interconnections must be provided to implement redundancy in programmable logic devices that contain programmable logic that is organized in this way.
It is therefore an object of the present invention to provide a redundancy scheme in which the circuitry used to switch redundant circuitry into use and the interconnection patterns used to implement redundancy may be simplified and improved.
These and other objects of the invention are accomplished in accordance with the principles of the present invention by providing a programmable logic device in which redundant circuitry may be shifted into place to repair defective circuitry. The programmable logic device has rows and columns of programmable logic regions. One of the rows of programmable logic regions may be a redundant logic region. When a defect is detected in a row of the device, programming data that would otherwise have been loaded into that row is routed into normal rows without defects and the redundant row.
The programming data is shifted into the device using switching circuitry. Two data registers are associated with each row. One of the data registers in each row is loaded serially. The other data register in each row is loaded in parallel. In normal operation, switching circuitry connects the serially-loaded data registers in a chain, so that data may be loaded into the chain from a data input pin. After the data has been loaded in this way, the data is shifted into the other data registers in parallel. When a defect is detected in one of the rows, the switching circuitry is reconfigured using fuse logic. The manufacturer may configure the fuse logic using a laser. The fuse logic directs the switching circuitry to bypass the serial data register in the defective row. Programming data is instead loaded into the serial data registers in the good rows and in the redundant row.
Test registers may be provided to facilitate the unloading of test data from the device. Switching circuitry associated with test registers may be used to serially unload the test data through a single pin.
Each programmable logic region has input and output lines connected to horizontal and vertical conductors on the device by programmable connectors. The lines are connected to the conductors by patterns of programmable connectors that accommodate row shifting. For example, in each column, the patterns of the input lines from the horizontal and vertical conductors and the patterns of the output lines to the horizontal conductors may be the same for the programmable logic regions in each row.
The programmable connectors between the output lines and the vertical conductors may include normal programmable connectors and redundant programmable connectors. This allows the vertical output pattern of programmable connectors to vary from row to row, thereby increasing routing flexibility. The normal and redundant programmable connectors are programmed with programming data. When there is no row shifting the programming data configures particular normal programmable connectors associated with lines in unshifted rows to form electrical connections to the vertical conductors and the programming data inactivates the redundant programmable connectors. When there is row shifting, the programming data configures the redundant programmable connectors and some of the normal programmable connectors in each shifted row to make the electrical connections that would otherwise have been made by just the normal programmable connectors in the corresponding unshifted row.
Further features of the invention and its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.